(pressebox) Mountain View CA, 02.11.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of "Groovy Green [...]
Tag Archive > Verification Methodology
Rockchip Collaborates with Synopsys and Chartered to Achieve First-Pass Silicon Success
(pressebox) Fuzhou , P.r.c., / Mountain View, Calif., USA / Singapore, 03.08.2009, Fuzhou Rockchip Electronics Company, Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. today announced that Rockchip has achieved first-time silicon success on its next-generation multimedia system-on-a-chip (SoC), using a combination of Synopsys’ tools, intellectual property (IP) and services with Chartered’s 65-nanometer (nm) manufacturing [...]
Verivue Deploys VMM and Synopsys VCS Solution for Verification of Scalable Media Distribution Switch
(pressebox) Mountain View, Calif., USA, 30.04.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Verivue, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys’ DiscoveryTM Verification Platform, for the verification of their flagship product, [...]
Tego Standardizes on VMM and Synopsys VCS Solution to Speed Verification of Radio Frequency Identification Tags
(pressebox) MOUNTAIN VIEW, Calif., USA, 29.04.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Tego, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys’ DiscoveryTM Verification Platform, to verify their radio frequency identification (RFID) [...]
Industry’s First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available
(pressebox) Mountain View CA, 23.02.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the availability of the Verification Methodology Manual for Low Power (VMM-LP), the culmination of a collaborative effort between ARM, Renesas Technology and Synopsys to document a proven methodology for the comprehensive verification [...]
New DesignWare Verification IP Alliance Program Expands Availability of High-Quality VMM-Enabled Verification IP
(pressebox) Mountain View /Calif./ USA, 11.02.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the launch of its DesignWare® Verification IP (VIP) Alliance program with initial members eInfochips, a spec-to-system solutions company, and NoBug, a digital design, verification and EDA company. Both are current members of [...]
