(pressebox) Mountain View CA, 21.09.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced its new StarRC(tm) Custom parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design. By combining the gold standard Star-RCXT(tm) extraction technologies and the Raphael(tm) NXT 3D fast field [...]
Tag Archive > Synopsys Inc
TSMC Selects Synopsys HSIM Simulator for Sub-40nm Memory IP Characterization
(pressebox) Mountain View CA, 14.09.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC has adopted Synopsys’ HSIM® hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow. The HSIM simulator will be deployed for TSMC advanced SRAM compilers [...]
Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and 1.35V DDR3L
(pressebox) Mountain View CA, 09.09.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its DesignWare® DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY [...]
Renesas Technology Selects Synopsys Proteus OPC for 45-nm Node Production
(pressebox) Mountain View CA, 25.08.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Renesas Technology Corp., the world’s No.1 supplier of microcontrollers and one of the world’s premier semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys [...]
Rockchip Collaborates with Synopsys and Chartered to Achieve First-Pass Silicon Success
(pressebox) Fuzhou , P.r.c., / Mountain View, Calif., USA / Singapore, 03.08.2009, Fuzhou Rockchip Electronics Company, Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. today announced that Rockchip has achieved first-time silicon success on its next-generation multimedia system-on-a-chip (SoC), using a combination of Synopsys’ tools, intellectual property (IP) and services with Chartered’s 65-nanometer (nm) manufacturing [...]
Synopsys Introduces Galaxy Constraint Analyzer to Improve Designer Productivity
(pressebox) Mountain View, Calif., USA, 24.07.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today introduced Galaxy(tm) Constraint Analyzer, a new tool which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer is an intuitive tool [...]
Synopsys Galaxy Implementation Platform Supports TSMC 28-Nanometer Process Technology with Reference Flow 10.0
(pressebox) Mountain View CA., USA, 23.07.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Galaxy(tm) Implementation Platform supports TSMC’s 28-nanometer (nm) process technology with Reference Flow 10.0. Galaxy technologies featured in Reference Flow 10.0 include comprehensive 28-nm design rule support for place [...]
Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform
(pressebox) MOUNTAIN VIEW, Calif., USA, 01.07.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that ST-Ericsson has adopted Synopsys’ MVSIM low power dynamic verification solution for its STw8500 system-on-chip (SoC) platform for the mobile phone market. ST-Ericsson selected MVSIM for its proven ability to [...]
Aquantia Deploys Synopsys IC Validator and IC Compiler for 40nm Quad 10GBASE-T Design
(pressebox) Mountain View, CA, 29.06.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Aquantia, the leading innovator in 10GBASE-T networking, has deployed Synopsys’ recently announced IC Validator, the newest addition to the Galaxy(tm) Implementation Platform, into production use at 40 nanometers (nm). IC [...]
Synopsys führt den Impuls von Galaxy-Custom-Designer mit der 2009.06-Release weiter
(pressebox) München, 16.06.2009, Synopsys, Inc. (Nasdaq: SNPS), weltweit führender Anbieter von Software und IP zum Entwurf und zur Fertigung integrierter Schaltungen, gibt bekannt, dass erweiterte Möglichkeiten für die Analog-Simulation und Layout-Generierung in seiner Implementierungslösung Galaxy-Custom-Designer(tm) verfügbar sind. Die neuen Features der Release 2009.06 sorgen für Produktivitätsfortschritte für Entwickler analoger Schaltkreise und Layout-Ingenieure. Synopsys deckt dadurch [...]
Synopsys IC Compiler with Zroute Technology Achieves Successful Tapeout for InfineonAutomotive Microcontroller
(pressebox) Mountain View, CA, 09.06.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that IC Compiler with Zroute technology drove silicon success for automotive microcontrollers of Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY), a world leading automotive semiconductor provider. IC Compiler’s Zroute provided a [...]
TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
(pressebox) Mountain View,Calif.,USA, 09.06.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC selected Synopsys’ Galaxy(tm) Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys’ Design Compiler® synthesis and IC Compiler physical implementation [...]
Synopsys schafft durch das System-Level-Catalyst-Programm Kompatibilität beim Systementwurf
(pressebox) München, 08.06.2009, Synopsys, Inc. (NASDAQ:SNPS), weltweit führender Anbieter von Software und IP zum Entwurf und zur Fertigung integrierter Schaltungen, stellt sein System-Level-Catalyst-Programm vor, das die Einführung des Entwurfs und der Verifikation auf Systemebene beschleunigen soll. Das Programm ist offen für Electronic-Design-Automation-(EDA)-Firmen, Anbieter von Intellectual Property (IP), Embedded-Software-Entwickler sowie Dienstleister. Es hat zum Ziel, gemeinsamen [...]
Synopsys’ Eclypse Low Power Solution Enables Fujitsu Microelectronics to Cut Design Cycle by 30 Percent
(pressebox) Mountain View CA, 03.06.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Fujitsu Microelectronics Limited (FML) has deployed Synopsys’ Galaxy(tm) Implementation Platform, for use with its low power digital electronics and mobile application ICs (integrated circuits). Fujitsu Microelectronics engineers used IEEE 1801 [...]
Synopsys Announces First DDR3 IP Verified in Silicon at 1600 Megabits per Second
(pressebox) Mountain View CA, 03.06.2009, Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its DesignWare® DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Megabits per second (Mbps), the maximum data-rate of the [...]
