PRESSEMITTEILUNGEN

MÜNCHEN, Deutschland und MOUNTAIN VIEW, Kalifornien, May 23, 2011 (ots/PRNewswire) — – Integrierte Entwufs- und Testtechnologie verbindet Algorithmenentwurf und Systemintegration für LTE / LTE-Advanced – Rohde & Schwarz und Synopsys arbeiten zusammen, um den Entwurf und die Verifikation von LTE / LTE-Advanced Systemen zu beschleunigen, und die Sicherheit bzgl. der Standardkompatibilität zu erhöhen. – Synopsys [...]

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Amp, Bibliotheken, Ein, First Test, Hardware, Konfiguration, Mountain View, Ots, Prnewswire, Rohde Schwarz, Synopsys Inc, Unmittelbar

Mountain View, Kalifornie, June 14, 2010 (ots/PRNewswire) – Synopsys, Inc. , weltweit führender Anbieter von Software und IP zum Entwurf, zur Verifikation und zur Fertigung integrierter Schaltungen, hat heute die neue PrimeTime(TM)-HyperScale-Technologie vorgestellt, die eine Statische Timing-Analyse (STA) für mehr als 500 Millionen Instanzen ermöglicht. Die PrimeTime-HyperScale-Technologie gibt Entwicklungsingenieuren den erforderlichen Einblick, um viele der [...]

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Aspx, Constraints, FüHrender Anbieter, Hyperscale, June 14, Mehr Als, Mountain View, Ots, Primetime, Prnewswire, Synopsys Inc, Timing Closure

Mountain View, Kalifornien, April 19, 2010 (ots/PRNewswire) – Synopsys, Inc. , ein weltweit führender Anbieter von Software und IP zum Entwurf, zur Verifikation und zur Fertigung integrierter Schaltungen, hat heute die HAPS(R)-60-Serie seiner Rapid-Prototyping-Systeme vorgestellt. Es handelt sich um eine umfassende Lösung zur Vereinfachung des Entwurfs und der Verifikation komplexer Systems-On-Chip. Die HAPS-60-Serie, Teil der [...]

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(pressebox) Mountain View CA, 03.11.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX® automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high-quality manufacturing tests. Stringent quality goals combined with [...]

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Arrow Electronics, Asic Design Engineers, Asic Designers, Automatic Test, Core Machines, Custom Logic, Design Complexity, Design Verification, Fault Coverage, Implementation Platform, Mountain View Ca, Physical Implementation, Processor Cores, Quality Goals, Scan Insertion, Semiconductor Design, Synopsys Inc, Test Pattern Generation, Test Quality, Tetramax Atpg

(pressebox) Mountain View CA, 02.11.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of "Groovy Green [...]

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Board Connectors, Carbon Design, Catalyst Program, Eda Interoperability, Eda Standards, Eda Tool Developers, Electronic Design Automation, Golden Reference, Green Computing, Interoperability Forum, Keynote Speaker, Mountain View Ca, Physical Verification, Prototyping Board, Semiconductor Design, Sun Microsystems, Synopsys Inc, Vendor Tools, Verification Methodology, Vmm

(pressebox) MOUNTAIN VIEW, Calif., USA, 02.11.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced a new capability in DFTMAX(tm) compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a [...]

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Data Volume, Design Complexity, Design Verification, Form Factors, Mixed Signal, Pin Count, Pin Interface, Quality Goals, Reliable Products, Scan Technology, Semiconductor Design, Synopsys Inc, Target, Test Coverage, Test Methodologies, Test Pins, Test Quality, Test Time, Tetramax Atpg, Wolfson Microelectronics

(pressebox) Mountain View CA, 29.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of the new DesignWare® USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in [...]

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Consumer Applications, Customer Designs, Design Verification, Designware, Host Port, Mobile Internet Devices, Mobile System, Mountain View Ca, Nanometer, Nasdaq, Pc Host, Pin Count, Power Efficiency, Power Management Features, Power Sources, Semiconductor Design, Standby Power Consumption, Synopsys Inc, Usb Otg, Wall Charger

(pressebox) Mountain View CA, USA, 28.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that NVIDIA Corp., has adopted Synopsys’ Yield Explorer solution for yield analysis and yield ramp. NVIDIA, which invented the graphics processing unit, selected Yield Explorer because of its ability to [...]

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Analysis Applications, Characterisation, Design Verification, Diagnostics Capabilities, Failure Mechanisms, Gigabytes, Graphics Processing Unit, Mountain View Ca, Nanometer, Nvidia Corp, Operational Efforts, Production Ramp, Root Cause Analysis, Semiconductor Design, Synopsys Inc, Test Domains, Test Floor, Today Announced That, Volume Production, Yield Management

(pressebox) Mountain View CA, USA, 28.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of its 40th audio codec IP with the release of the DesignWare® 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process. Synopsys has been a leading [...]

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Analog To Digital, Analog To Digital Converters, Audio Capabilities, Audio Codec, Audio Functions, Digital To Analog Converters, Integration Risk, Ip Solution, Line Headset, Microphone Amplifiers, Mountain View Ca, Mutual Customers, Semiconductor Design, Silicon Success, Smic, Soc Designs, Speaker Drivers, Synopsys Inc, Technical Support Experts, Term Collaboration

(pressebox) MOUNTAIN VIEW, Calif., USA, 26.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the expansion of its verification collaboration with Freescale. The integration of complex hardware enabled by Moore’s law, IP, and embedded software content in modern devices is causing a rapid increase [...]

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Art Environment, Collaboration Agreement, Dan Cronin, Design Verification, Early Adopters, Freescale Semiconductor, Freescale Semiconductor Inc, Functional Verification, Law Ip, Manoj, Network Solutions, Performance Efficiency, Production Schedules, Quot Quot, Rapid Increase, Semiconductor Design, Senior Vice President, Software Content, Synopsys Inc, Verification Group

MÜNCHEN, October 12 (ots/PRNewswire) – – Einzigartige M-language- und modell-basierte Lösung erreicht eine bis zum Faktor 10 höhere Produktivität für Entwickler von Kommunikations- und Multimedia-Systemen Synopsys, Inc. (Nasdaq: SNPS), ein weltweit führender Anbieter von Software und IP zum Entwurf, zur Verifikation und zur Fertigung integrierter Schaltungen, hat heute seine HLS-Lösung (High-Level-Synthesis) Synphony vorgestellt. Diese Lösung [...]

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Confirma, Innovator, Level Synthesis, Multimedia, Nasdaq, Prnewswire, Rapid Prototyping, Rtl Code, Synopsys Design Compiler, Synopsys Inc, Synphony, Synplify, Tm System, Vcs

(pressebox) Mountain View CA, 07.10.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that STMicroelectronics (ST) has achieved first-pass silicon success for its STM32 Connectivity Line of system-on-chips (SoCs) utilizing the Synopsys DesignWare® USB 2.0 On-The-Go (OTG) and Ethernet digital controllers. ST, a global [...]

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Audio Applications, Design Verification, Designware, Digital Controllers, Digital Ip, Ethernet Interface, Ip Providers, Ip Solution, Ip Solutions, Ip Vendors, Mountain View Ca, Otg, Precision Time, Product Differentiation, Ruat, Semiconductor Design, Semiconductor Solutions, Silicon Success, Synopsys Inc, Time Protocol

(pressebox) Mountain View, CA, 06.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL), a leading government laboratory pursuing research in photovoltaic devices, has adopted Synopsys’ Sentaurus TCAD for simulating solar cell characteristics to [...]

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Cadmium Telluride, Carbon Emissions, Cell Characteristics, Cell Models, Material Layers, Mountain View Ca, National Renewable Energy, National Renewable Energy Laboratory, Nrel Scientists, Performance Metrics, Photovoltaic Devices, Physical Mechanisms, Principal Scientist, Renewable Energy Laboratory, Renewable Sources Of Energy, Semiconductor Design, Solar Cell Performance, Solar Cells, Solar Radiation Incident, Synopsys Inc

(pressebox) Mountain View, CA, 30.09.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Common Platform technology alliance, a unique technology collaboration between IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, has qualified IC Validator for 32-nanometer (nm) process design rule checking on Common [...]

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Alliance Companies, Chartered Semiconductor Manufacturing, Design Verification, Flexible Programming Language, Henry Law, Implementation Platform, Mountain View Ca, Physical Verification, Platform Technology, Productivity Advantages, Productivity Benefits, Samsung Electronics, Semiconductor Design, Signoff, Synopsys Inc, Technology Alliance, Technology Collaboration, Today Announced That, Turnaround Time, Validator