Tag Archive > Semiconductor Design

Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics

(pressebox) Mountain View CA, 03.11.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX® automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high-quality manufacturing tests. Stringent quality goals combined with [...]

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Synopsys EDA Interoperability Forum to Feature Subodh Bapat Keynote on Green Computing

(pressebox) Mountain View CA, 02.11.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of "Groovy Green [...]

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Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test

(pressebox) MOUNTAIN VIEW, Calif., USA, 02.11.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced a new capability in DFTMAX(tm) compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a [...]

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Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes

(pressebox) Mountain View CA, 29.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of the new DesignWare® USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in [...]

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NVIDIA adopts Synopsys Yield Explorer to reduce time to volume

(pressebox) Mountain View CA, USA, 28.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that NVIDIA Corp., has adopted Synopsys’ Yield Explorer solution for yield analysis and yield ramp. NVIDIA, which invented the graphics processing unit, selected Yield Explorer because of its ability to [...]

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Synopsys announces 40th DesignWare audio codec IP

(pressebox) Mountain View CA, USA, 28.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of its 40th audio codec IP with the release of the DesignWare® 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process. Synopsys has been a leading [...]

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Freescale and Synopsys Announce Multi-year Strategic Collaboration Agreement to Increase Verification Productivity

(pressebox) MOUNTAIN VIEW, Calif., USA, 26.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the expansion of its verification collaboration with Freescale. The integration of complex hardware enabled by Moore’s law, IP, and embedded software content in modern devices is causing a rapid increase [...]

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Synopsys DesignWare USB 2.0 and Ethernet IP Enables First-Pass Silicon Success for STMicroelectronics

(pressebox) Mountain View CA, 07.10.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that STMicroelectronics (ST) has achieved first-pass silicon success for its STM32 Connectivity Line of system-on-chips (SoCs) utilizing the Synopsys DesignWare® USB 2.0 On-The-Go (OTG) and Ethernet digital controllers. ST, a global [...]

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Synopsys’ Sentaurus TCAD Used to Simulate Solar Cell Performance Characteristics at NREL

(pressebox) Mountain View, CA, 06.10.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL), a leading government laboratory pursuing research in photovoltaic devices, has adopted Synopsys’ Sentaurus TCAD for simulating solar cell characteristics to [...]

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Common Platform Alliance Qualifies Synopsys IC Validator for 32-nm Design Rule Checking

(pressebox) Mountain View, CA, 30.09.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Common Platform technology alliance, a unique technology collaboration between IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, has qualified IC Validator for 32-nanometer (nm) process design rule checking on Common [...]

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Synopsys Unveils StarRC Custom Parasitic Extraction Solution

(pressebox) Mountain View CA, 21.09.2009, Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced its new StarRC(tm) Custom parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design. By combining the gold standard Star-RCXT(tm) extraction technologies and the Raphael(tm) NXT 3D fast field [...]

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ROHM Semiconductor gründet European Design Centre (EUDC)

(pressebox) Willich-Münchheide, 17.09.2009, ROHM Semiconductor gibt die Gründung des neuen European Design Centre (EUDC) bekannt, das Kunden in Europa mit speziellen Produkten, Projektmanagement und Design-In-Unterstützung versorgen wird. Das am Standort Wilich-Münchheide angesiedelte EUDC hat am 1. September 2009 seinen Betrieb aufgenommen. "Das neue Designzentrum wird unsere Bandbreite an innovativen, auf die Anforderungen unserer europäischen Kunden [...]

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TSMC Selects Synopsys HSIM Simulator for Sub-40nm Memory IP Characterization

(pressebox) Mountain View CA, 14.09.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC has adopted Synopsys’ HSIM® hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow. The HSIM simulator will be deployed for TSMC advanced SRAM compilers [...]

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Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and 1.35V DDR3L

(pressebox) Mountain View CA, 09.09.2009, Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its DesignWare® DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY [...]

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Renesas Technology Selects Synopsys Proteus OPC for 45-nm Node Production

(pressebox) Mountain View CA, 25.08.2009, Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Renesas Technology Corp., the world’s No.1 supplier of microcontrollers and one of the world’s premier semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys [...]

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