PRESSEMITTEILUNGEN

(pressebox) Eindhoven/the Netherlands, 29.09.2009,

JTAG Technologies, a leading provider of IEEE Std. 1149.1 solutions for testing and programming high-density PCBs, announces a further extension of its line of high-performance boundary-scan IEEE Std. 1149.1 controllers. Known as the DataBlaster JT 37×7/PCIe the new unit offers support for the now popular PCI-express slot format found extensively in today’s PCs. The PCIe bus is a high-speed serial replacement of the older parallel PCI bus.

Following industry demands JTAG Technologies have developed the new, boundary-scan, controller to satisfy the burgeoning requirements for high speed In-System Programming (ISP) of flash memories and CPLDs and complex digital circuit testing. The new DataBlaster JT 37×7/PCIe offers the user sustained test clock speeds of up to 40MHz by use of JTAG Technologies proprietary ETTT (Enhanced Throughput Technology) system and features a flash image buffer memory which may be expanded to 128 Mbits.

Supplied with the complementary QuadPODT, also from JTAG Technologies, the new DataBlaster/PCIe offers four synchronised TAPs (Test Access Ports) able to support multi-TAP test targets (UUT’s) or gang programming of four single TAP targets. QuadPODT is ‘low-voltage ready’ and the advanced technology also allows maximum test speeds at the target by incorporating high-speed signal conditioning, logic threshold adjustments and cable delay compensations in a compact, remote, extension module.

The scalable DataBlaster JT 37×7/PCIe range starts with the low-cost entry model JT 3707/PCIe, ideal for high-speed 40MHz test applications and in-system PLD programming. Companion models JT 3717/PCIe and JT 3727/PCIe, optionally fitted with an ETTT module for flash ISP, support high-throughput flash programming as well as test and PLD programming. The flexible nature of of ETTT allows it to support memories with various data-bus widths from 1-bit to 64Kbit.

DataBlaster/PCIe units are fully compatible with all revisions of JTAG Technologies test and ISP tools, such as JTAG ProVision and the former ‘Classic’ family of development and run-time packages.

Trackback URL

Boundary Scan, Buffer Memory, Bus Widths, Clock Speeds, Entry Model, Flash Image, Flash Memories, Flexible Nature, High Throughput, Image Buffer, Industry Demands, Jtag Technologies, New Express, Pld Programming, Scan Controller, Slot Format, Speed Signal, Test Clock, Test Speeds, Test Targets